module dMem(
    input           clock,
    input   [31:0]  address,
    input   [31:0]  data_in,
    input           memRead,
    input           memWrite,
    output  [31:0]  data_out
);

// Create 256 memory locations
reg [7:0]  memory  [0:31];

always @(posedge clock)
begin
    if (memWrite)
    begin
        memory[address+3] <= data_in[31:24];
        memory[address+2] <= data_in[23:16];
        memory[address+1] <= data_in[15:8];
        memory[address]   <= data_in[7:0];
    end
end
   
assign data_out = (memRead) ? {memory[address+3], memory[address+2], memory[address+1], memory[address]} : 32'b0;
endmodule